1. Field of the Invention
This invention relates to computer system designs, and in particular relates to the design of multiple level cache systems.
2. Description of the Related Art
A cached memory system improves the performance of a computer system by exploiting locality of reference. A cache memory is typically implemented by more costly components or circuits which are capable of higher performance (i.e. shorter response time) than those implementing the main memory. By storing in the cache memory copies of small groups of data likely to be accessed repeatedly, performance of the computer system can be enhanced. Extended this concept further, performance of a cache system can be enhanced by having multiple levels of cache memory.
Because a cached memory system contains one or more copies of data stored in the main memory, to ensure that the correct data is provided in a subsequent reference (i.e. to ensure "data coherency"), an update to the data at a memory location must be reflected in all copies of the data residing in the cache memory system. One method for providing data coherency is the cache "write-through" policy, which requires that an update to a datum be immediately written out to the main memory and, at the same time, all other copies of the datum residing in the cached system be invalidated or updated. However, in a shared memory multiprocessor system, in which each processor has a private cache memory, a difficulty relating to data coherency arises. In such a system, in order to maintain data consistency, when a datum in the main memory is updated, it is necessary to update or invalidate all copies of the datum in each processor's private cache memory.
Another instance causing a data coherency problem results from a peripheral device moving data into the main memory system through direct memory access (DMA). In this instance, it is necessary to update all levels of the cache memory system.
Because the central processing unit (CPU) of a computer system often operates asynchronously with the memory system, first-in-first-out (FIFO) buffers are often interposed between the CPU and the memory. During a write operation, instead of waiting for completion of a write operation in the main memory, a CPU simply writes the data into a FIFO. At a subsequent time, the memory controller retrieves the datum from the FIFO and completes the write operation ("retires") in the main memory. Under such a scheme, however, a read access to a memory location must ascertain that there is not an incomplete pending write operation to the memory location, so as to prevent stale data from being read into the CPU. This scheme is further complicated in a shared memory multiprocessor system which allows each processor in the multiprocessor system to write into the same memory space.